1. Technical Field
The present disclosure relates generally to integrated circuit (IC) design. More particularly, and not by way of any limitation, the present disclosure is directed to a system and method for verifying Intellectual Property (IP) components in an embedded IC such as a System-On-Chip (SOC) design.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, non-volatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that complex SOCs of today may contain numerous third-party IP modules, possibly from different vendors. Usually an IP design package comprises multiple modules that are wrapped by the IP's top-level module. The IP package may be verified as a standalone design prior to integration into a SOC. However, in some instances, a user (i.e., system integrator) may wish to partition the IP into separate modules while integrating into its SOC. The necessity of such a partitioning is typically caused by SOC design flow peculiarities, mapping, power planning and place-and-routing considerations, and the like. In this case, the customer (i.e., user) does not use the IP's top-level module; rather, the individual IP modules are directly integrated into user's design hierarchy. After integration of such third-party IP modules into the SOC design net, there is, however, a potential risk of compromising the IP functionality. To be sure that the IP modules are properly functional, the SOC design net between instances of the IP modules must be established exactly in the same way it was established within the IP's top-level module. The violations of interconnections that can appear in the SOC design net are nearly impossible to detect using system-level functional simulation, especially when the IP is deeply embedded into the SOC. Additionally, the functional tests require costly long-running simulations. On the other hand, formal equivalence verification tools may offer a viable alternative to functional simulation. However, use of equivalence verification tools requires investments and deep knowledge of the integrated third-party IP structure.